The current invention relates to a silicon on higher thermal conductive multi-layer composite wafer and methods thereof.
In the specification and claims which follows, the expression “semiconductor” is intended to interchangeably mean “semiconductor material”, such as, but not limited to: silicon and gallium-nitride; which are typically produced in a wafer shape and serve as a base or substrate material, as known in the art in the semiconductor industry. The terms “silicon” or “Si” are likewise intended to mean a silicon crystalline material, typically produced in a wafer shape and serving as a base or substrate material, as known in the art in the semiconductor industry. “SiC” is intended to mean a silicon carbide material, likewise typically produced in a wafer shape and serving as a base or substrate material, as known in the art.
The semiconductor integrated circuit (IC) industry has been driven for decades by the capability to shrink devices and to package them into increasingly higher circuit densities. The resultant power dissipation of such silicon-based devices poses a risk of yielding thermal levels which are incompatible with proper device operation.
Other developments related to leakage current management have led to the introduction of a family of substrates called Silicon-on-Insulator (SOI). This type of substrate offers many advantages for operating high-power devices, except that the insulator layer typically has poor thermal conductivity, which can yield high device operating temperature and thus limit device density.
An attractive solution to allow maintaining device performance at a lower operating temperature is to use a composite wafer as a starting material. Such an approach is proposed in U.S. Pat. No. 8,153,504, whose disclosure is incorporated herein by reference, in which Allibert et al. describe a process for manufacturing a composite substrate comprising bonding a first substrate onto a second semiconducting substrate, characterized in that the process includes, before bonding, the formation of a bonding layer between the first and the second substrate, the bonding layer comprising a plurality of islands distributed over a surface of the first substrate in a determined pattern and separated from one another by regions of a different type, which are distributed in a complementary pattern, wherein the islands are formed via a plasma treatment of the material of the first substrate.
An approach described by Alibert et al. hereinabove addresses materials science issues but has not been applied in industry due to the complexity and associated high cost of the proposed manufacturing process of the composite substrate.
Among additional prior art touching upon these and similar problems and solutions are:
Kawamoto et al., in U.S. Pat. No. 8,507,922, whose disclosure is incorporated herein by reference, describe a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate is provided with a first silicon carbide layer (1), which is composed of a polycrystalline silicon carbide, and a second silicon carbide layer (2), which is composed of polycrystalline silicon carbide formed on the surface of the first silicon carbide layer. The second silicon carbide layer (2) has a high-frequency loss smaller than that of the first silicon carbide layer (1), the first silicon carbide layer (1) has a thermal conductivity higher than that of the second silicon carbide layer (2), and on the surface side of the second silicon carbide layer (2), the high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less, and the thermal conductivity is 200 W/mK or more.
U.S. Pat. No. 8,470,687, whose disclosure is incorporated herein by reference, in which Forbes et al. describe a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer.
Matsushita et al., in U.S. Pat. No. 4,571,610, whose disclosure is incorporated herein by reference, describe semiconductor devices in which an electrical insulating substrate is made of a sintered silicon carbide body having thermal conductivity of at least 0.4 cal/cm.-sec.-degree C. at 25 degrees C.
U.S. Pat. No. 6,309,766, whose disclosure is incorporated herein by reference, in which Sullivan describes a substrate made of polycrystalline. beta. SiC and having an essentially pore-free surface. The substrate is adapted for use as a wafer component to support different thin films as part of manufacturing for discrete or integrated circuit electronic devices. The substrate comprises a polycrystalline silicon carbide outer surface with {111} crystal planes exposed on the working surface, the outer surface is essentially pore free or without exposed pores, scratches, steps or other such depressions or discontinuities on the surface of the substrate having at least one dimension larger than 2.54 microns, and no non-stoichiometric silicon or carbon other than that which may be residual from the process of making silicon carbide ceramic material.
Yerman et al., in U.S. Pat. No. 4,816,422, whose disclosure is incorporated herein by reference, describe a method for fabricating a composite semiconductor from a plurality of substantially identical individual semiconductor devices formed on a common semiconductor wafer includes testing the devices on the wafer to generate a positional mapping of acceptable and non-acceptable devices, dividing the wafer into a plurality of areas of arbitrary size, connecting corresponding contact pads on only the acceptable devices within a given area to each other via common conductive paths which are supported on a dielectric film covering the pads, the film having appropriately located holes filled with conductive material to electrically couple the common conductive paths and the underlying contact pads of only the acceptable devices. The devices within a given area are intercoupled in a manner to form an operational array; single or multiple arrays may be coupled together to form a composite package having common external contacts and heat sink supports.
U.S. Pat. No. 3,954,483, whose disclosure is incorporated herein by reference, in which Prochazka describes a dense silicon carbide material having improved electrically conducting properties is disclosed which is prepared by forming a homogeneous dispersion of silicon carbide, a sufficient amount of boron nitride, and optionally a boron containing additive and hot pressing the dispersion at a sufficient temperature and pressure whereby a dense substantially nonporous ceramic is formed. The silicon carbide material can be machined by electrical discharge machining or by electrochemical machining.
Additionally, Ghyselen et al., in U.S. Pat. Nos. 7,262,113 and 7,422,957 whose disclosures are incorporated herein by reference, describe, inter alia, methods for fabricating final substrates for use in optics, electronics, or optoelectronics are described. The method includes forming a zone of weakness beneath a surface of a source substrate to define a transfer layer; detaching the transfer layer from the source substrate along the zone of weakness; depositing a useful layer upon the transfer layer; and depositing a support material on the useful layer to form the final substrate. The useful layer may be deposited on the transfer layer before or after detaching the transfer layer from the source substrate. The useful layer is typically made of a material having a large band gap, and comprises at least one of gallium nitride, or aluminum nitride, or of compounds of at least two elements including at least one element of aluminum, indium, and gallium. The zone of weakness may advantageously be formed by implanting atomic species into the source substrate.
As noted previously, prior art solutions, including those by Ghyselen et al, of Soitec Silicon on Insulator Technologies SA hereinabove have not been applied in industry due to the complexity and associated high cost of the proposed process of manufacturing the composite substrate.
Reference is currently made to FIGS. 1A-1B, which are schematic illustrations showing major steps of a Prior Art manufacturing process 5 of Silicon on Poly Silicon Carbide (SiC) wafers, such as described in the Soitec reference hereinabove. Process 5 starts with two parallel manufacturing paths, shown in the figure, as follows:                1. A silicon wafer 6 (also referred hereinbelow as a “host” silicon wafer) is purchased. The wafer typical cost is approximately $50.        2. Silicon wafer 6 then undergoes H/He implantation 7, as known in the art, the current step costing about $100.        3. A layer of Si thermal oxide (SiO2) 8 is then deposited, on the silicon wafer, yielding wafer 10 as indicated in the figure. The oxide step costs typically $50.        4. In parallel to steps 1-3 above, a Poly Silicon Carbide (pSiC) wafer 16 is purchased. The typical cost of the pSIC wafer is approximately $500.        5. pSiC wafer 16 then undergoes a-Si CVD deposition and CMP polishing 17, both as known in the art; the current step costing about $100.        6. A layer of Si thermal oxide (SiO2) 18 is then deposited, yielding wafer 20, as indicated in the figure. The oxide step costs typically $50.        7. At this point, wafer 10 (from steps 1-3) and wafer 20 (from steps 4-6) are bonded, with respective oxide layers of each bonded to each other. This creates a bonded wafer 22; and the current step costs approximately $50.        8. Continuing with process 5 (referring to FIG. 1B) host silicon wafer 6 is removed from bonded wafer 22. The current step costs about $50.        9. Following removal of the host silicon wafer, the remaining bonded wafer undergoes CMP polishing, as known in the art, yielding a completed Silicon on Poly Silicon Carbide wafer 30. The current CMP polishing steps costs approximately $50.        
Applying process step costs known in the art, as described in FIGS. 1A-1B hereinabove, it is estimated that the prior art process described hereinabove yields starting-wafer/starting material costs of at least $1,000, which is an excessively high cost.
There is therefore a need to maintain device performance at a lower operating temperature using a composite wafer as starting material—and to do so in a cost-effective manner commensurate with modern semiconductor fabrication constraints to enable a cost-effective process.